{"id":6598,"date":"2021-05-26T22:32:50","date_gmt":"2021-05-26T17:02:50","guid":{"rendered":"https:\/\/trident.ac.in\/placementnotice\/?p=6598"},"modified":"2021-05-26T22:49:12","modified_gmt":"2021-05-26T17:19:12","slug":"openfive-hiring-interns-2021-yop","status":"publish","type":"post","link":"https:\/\/trident.ac.in\/placementnotice\/openfive-hiring-interns-2021-yop\/","title":{"rendered":"OpenFive Hiring Interns \u2013 2021 YOP || Register on or before 10:00PM, 28th may 2021."},"content":{"rendered":"

Dear Students,<\/p>\n

Greetings from OpenFive!<\/p>\n

OpenFive<\/strong>\u00a0has shown interest to hire\u00a0Interns<\/strong>\u00a0from\u00a0ECE, <\/strong>EEE, Electrical and Instrumentation 2021 pass outs only.\u00a0 <\/strong><\/p>\n

Please find the brief of the organization.<\/p>\n

OpenFive is a solution-centric silicon company that is uniquely positioned to design processor agnostic SoC architecture, with customizable and differentiated IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions. OpenFive develops domain-specific SoC architecture based on high-performance, highly efficient, cost-optimized IP to deliver scalable, optimized, differentiated silicon. OpenFive employees work collaboratively to deliver end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation, and Manufacturing disciplines required to deliver high-quality silicon to semiconductor companies and systems manufacturers. Focused on delivering silicon for customer specifications, no two projects are identical keeping things fresh and offering opportunities to continually develop new skills and meet more people in the semiconductor industry.<\/p>\n

Website: https:\/\/openfive.com\/\/<\/a> https:\/\/www.sifive.com\/<\/a><\/p>\n

Please find the required details:<\/p>\n

Eligibility: BTech\/MTech in ECE, EEE, or\u00a0Electrical and Instrumentation 2021 passing out Only with 70% throughout in academics and zero active backlogs.<\/strong><\/p>\n

Position –\u00a0<\/strong>Intern<\/p>\n

Duration \u2013\u00a0<\/strong>6-month internship (conversion based on performance)<\/p>\n

Location \u2013\u00a0<\/strong>Bangalore and Pune<\/p>\n

Stipend –<\/strong>\u00a0INR 25K per month during the internship<\/p>\n

PFB the Job Description: <\/u><\/strong><\/p>\n

Note:- Please send the student data showing their preferences for the JD.<\/p>\n

 <\/p>\n

1:- FPGA Engineer<\/strong><\/p>\n

 <\/p>\n

1) Very good knowledge of at least one hardware description language (Verilog, VHDL)<\/p>\n

2) Very good knowledge of System Verilog, UVM is a plus.
\n3) Very familiar with Altera’s or Xilinx’s build flow including design entry in Verilog, synthesis, place, and route, timing constraints, and timing closure
\n4) Hands-on with lab FPGA debug methodologies, such as ChipScope, SignalTap, or others
\n5) Hands-on experience with lab debug the equipment, such as oscilloscopes and logic analyzers
\n6) Good understanding of computer architectures
\n7) Experienced in designing digital circuits
\n8) Experienced in testing digital circuits in both simulation and hardware
\n9) Expertise with C\/C++<\/p>\n

10) Proven experience in FPGA prototyping multi-million gate ASIC design<\/p>\n

11) Proven experience in manual\/automated design partitioning.
\n12) Very good understanding of AMBA Protocols
\n13) Experience with working in Linux environment<\/p>\n

14) Experience in bring-up of at-least one of the CPU architecture on FPGA like RISCV\/ARM\/MIPS CPU is a must.<\/p>\n

15) Experience in bring-up at at-least one high-speed interface on FPGA like USB, PCIe, Ethernet, MIPI is a must.<\/p>\n

16) Experience in the bring-up of DDR memory interfaces for FPGA is a must.<\/p>\n

 <\/p>\n

2:- FE:<\/strong><\/p>\n